Single-block virtual frame buffer translated to multiple physical blocks for multi-block display refresh generator

ABSTRACT

A graphics controller for a System-On-a-Chip (SOC) used with a battery-powered device allows for reduced-power display modes. The microprocessor writes to a frame buffer that is a single, contiguous address block in virtual memory. A memory management unit (MMU) translates frame-buffer address to multiple physical blocks. The graphics controller fetches pixels from the multiple physical blocks, including a block in an on-chip memory and a block in an external memory. In a low-power mode, pixels are only fetched from the lower-power on-chip memory and not the higher-power external memory. A smaller display window is defined and pixels outside the window are replaced by dummy data, .eliminating external-memory fetches. The smaller display window falls within the first block in the on-chip memory. Status and other information can be displayed in the smaller display window during stand-by modes, while a full-screen of data is displayed for full-power modes.

Notice: More than one reissue application has been filed for the reissueof U.S. Pat. No. 6,680,738. The reissue applications are applicationSer. No. 11/337,221 (“the '221 application”), filed Jan. 20, 2006, andthe present application, which is a divisional of the '221 application,filed herewith.

BACKGROUND OF INVENTION

This invention relates to computer-graphics systems, and moreparticularly to frame buffers split among multiple blocks in memory.

An interesting variety of small consumer devices are appearing. Portablecomputing and/or communication devices such as the personal digitalassistant (PDA), Pocket PC, and smart cellular phones have anastonishing computing power for such small devices. These portable,often hand-held, computing devices often use avery-large-scale-integration (VLSI) chip that includes a microprocessoror central processing unit (CPU), memory, and I/O controllers on asingle silicon chip known as a System-On-a-Chip (SOC).

These consumer devices run on battery power to achieve portability. Thebattery must be made small and light to keep the size and weight of theoverall device small. Such small batteries necessitate the use oflow-power chips including the SOC.

The SOC can include an on-chip static random-access memory (SRAM).Program running on the SOC's CPU can access data from an on-chipread-only-memory (ROM) and write data to the on-chip SRAM. Using theon-chip SRAM reduces power, since this avoids access cycles to anexternal dynamic-random-access memory (DRAM) that require more power todrive the larger off-chip capacitances.

Some accesses of the external DRAM may still be needed to load a verylarge program into the SRAM, or to fetch very large data files. Oncethese are stored and fetched, the external DRAM can be powered downwhile the program and frame buffer are located and executed within theon-chip SRAM. Use of the on-chip SRAM also improves performance, as SRAMaccess times are faster than access times to the external DRAM.

The SOC may include a graphics controller that continuously reads pixeldata from a frame buffer and sends these pixels off-chip from the SOC toa display. The display can be a small liquid crystal display (LCD) thatrequires little power, or other compact display. The frame buffer can bea portion of the on-chip SRAM that is written by the CPU when updatingthe display. Using the internal SRAM for the frame buffer can furthersave power, since external accesses of an external frame-buffer memoryare avoided.

However, larger, more colorful displays running at higher-resolutionmodes may require a large frame buffer to store a large number ofpixels. Higher-color modes require more storage bits per pixel, andhigher resolutions have more pixels to store. The on-chip SRAM may needto be enlarged to provide sufficient capacity for these larger framebuffers. However, larger on-chip SRAMs increase the SOC die size andreduce manufacturing yield. The SOC may even become too expensive formany low-cost consumer devices.

For example, a display of 320×240 pixels having one byte per pixelrequires 76,000 bytes, which fits in a 100 Kilo-Byte (KB) SRAM. However,a more colorful display using 16 bits per pixel requires about 150 KB,which is larger than the 100 KB SRAM.

The frame buffer could be split among the on-chip SRAM and the externalDRAM. However, all software programs running on the CPU expect the framebuffer to be a single, continuous block of address. Re-writing the manyprograms that can run on the CPU to allow for a split frame buffer isnot practical. Programs are written expecting a conventional framebuffer with a contiguous block of addresses.

What is desired is a SOC that supports a frame buffer that can be splitamong multiple blocks of memory in the internal SRAM and the externalDRAM. A graphics controller that can re-assemble pixels from themultiple blocks is desirable. A SOC that has a high-power display modethat splits the frame buffer between the on-chip SRAM and the externalDRAM, and with a low-power display mode that only uses the on-chip SRAMis desired. It is further desired that the frame buffer appear to be asingle, contiguous block of memory to programs executing on the CPU.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a block diagram of a System-On-a-Chip (SOC) with a multi-blockframe buffer.

FIG. 2 is a memory-map diagram showing CPU writes to the frame buffer.

FIG. 3 is a memory-map diagram showing display-refresh fetches from themulti-block frame buffer.

FIG. 4 shows page translation.

FIG. 5 is a diagram of refresh address generation for fetchingframe-buffer pixels from multiple physical blocks.

FIG. 6 is a display-timing diagram showing a block ending in the middleof a display line.

FIG. 7 is a display-timing diagram showing a block ending after the endof a display line in the off-screen area.

FIG. 8A shows a display that is refreshed with pixels from the on-chipSRAM and from the external SDRAM.

FIG. 8B shows a reduced-size display mode that is refreshed with pixelsfrom the on-chip SRAM.

DETAILED DESCRIPTION

The present invention relates to an improvement in frame buffers. Thefollowing description is presented to enable one of ordinary skill inthe art to make and use the invention as provided in the context of aparticular application and its requirements. Various modifications tothe preferred embodiment will be apparent to those with skill in theart, and the general principles defined herein may be applied to otherembodiments. Therefore, the present invention is not intended to belimited to the particular embodiments shown and described, but is to beaccorded the widest scope consistent with the principles and novelfeatures herein disclosed.

FIG. 1 is a block diagram of a System-On-a-Chip (SOC) with a multi-blockframe buffer. SOC 10 is a single-chip system that communicates withexternal peripherals 26 and display 29. CPU 12 executes programinstructions from ROM. 16 or from internal on-chip SRAM 22, or fromexternal synchronous DRAM (SDRAM) 28 through external memory controller20. Memory management unit (MMU) 14 translates logical addresses fromCPU 10 into physical addresses. MMU 14 can perform memory-page swappingand other functions.

Peripherals 26 can include a keypad or pointing device that inputscommands or selections from a user. Peripherals 26 can include otherdevices, such as a speaker, light-emitting diode lights, cableconnectors, etc. I/O controller 18 has registers that can be read andwritten by CPU 12 over internal bus 15 to communicate with and controlperipherals 26. Timers, direct-memory access (DMA), or other I/Ocontroller functions may be included in I/O controller 18.

Graphics display controller 24 drives a stream of pixels to externaldisplay 29 to refresh the display. These pixels are fetched from a framebuffer in on-chip SRAM 22 for low-power display modes when the entireframe buffer fits inside SRAM 22. However, for higher-resolution,higher-color, higher-power display modes the frame buffer does notcompletely fit in SRAM 22. Instead, the frame buffer is divided amongtwo or more blocks. At least one block is in SRAM 22, but one or moreother blocks are located in external SDRAM 28.

Graphics display controller 24 contains address-generation andboundary-checking logic to fetch some pixels from SRAM 22, while otherpixels are fetched from SDRAM 28 using external memory controller 20.

Programs running on CPU 12 update the display by writing pixels to asingle-block frame buffer in the logical address space. MMU 14translates these memory accesses from CPU 12 into the physical addressesof multiple blocks in SRAM 22 and SDRAM 28. Thus programs see a framebuffer with a single memory block, but graphics display controller 24sees a frame buffer with multiple memory blocks.

FIG. 2 is a memory-map diagram showing CPU writes to the frame buffer.Programs running on CPU 12 update the display by over-writing pixels inthe frame buffer. These programs write pixels using virtual addresswithin virtual address space 30. The frame buffer is a continuous blockof virtual address that include virtual blocks 32, 34. The startingaddress and size of the frame buffer are set by the application programor operating system depending on the current graphics mode.

Memory writes from CPU 12 are sent to MMU 14 before actually beingwritten to the frame-buffer memory. MMU 14 translates the virtualaddress from CPU 12 into a physical address for the memory. The physicaladdress is within physical address space 40, which includes both on-chipaddresses 90 in the on-chip SRAM, and external addresses 92 in theexternal SDRAM.

The frame buffer is split among two blocks in this example. Displayblock A is virtual block 32 in virtual address space 30, but physicalblock 42 in physical address space 40. Pixels to block 32 are translatedby MMU to addresses within block 42 so that the pixels are written toon-chip SRAM.

Display block B is virtual block 34 in virtual address space 30, butphysical block 44 in physical address space 40. Pixels to block 34 aretranslated by the MMU to addresses within block 44 so that the pixelsare written to the external SDRAM. Thus although blocks 32, 34 arecontinuous in virtual address space 30 accessed by programs, pixels arestored in separate physical blocks 42, 44 in different physical memorydevices.

FIG. 3 is a memory-map diagram showing display-refresh fetches from themulti-block frame buffer. Pixels are stored in multiple physical blocks42, 44 in physical address space 40.

Graphics display controller 24 reads pixels from physical block 42 withinternal addresses for the on-chip SRAM. These pixels are displayed asdisplay block 46 on display 29. Graphics display controller 24 alsoreads pixels from physical block 44 with external addresses for theexternal SDRAM. These pixels are displayed as display block 48 ondisplay 29. Thus Graphics display controller 24 reads separatephysical-memory blocks and combines them into a single frame of display.

FIG. 4 shows page translation. The MMU contains one or morepage-translation table 50. Table 50 contains translation entries such aslogical, physical address pairs. Recently-used entries can be cachedfrom a larger, more complete table.

Logical address 52 is generated by the CPU and contains aleast-significant-bits (LSB) portion known as offset 56. Themost-significant-bits (MSB) portion of logical address 52 is page baseaddress 54, or simply the page address.

Page base address 54 of logical address 52 is used to lookup an entry intranslation table 50. The entry for page base address 54 contains atranslated page address, which is output from table 50 as translatedpage address 55.

Physical address 53 is formed by concatenating translated page address55 with offset 56 from logical address 52, which is unchanged as offset57. Offset 56, 57 can be considered the address within a page that isidentified by page base address 54 in the logical address space, ortranslated page address 55 in the physical address space. In thisexample, offsets 56, 57 are 12 bits, for a page size of 4 KB.

FIG. 5 is a diagram of refresh address generation for fetchingframe-buffer pixels from multiple physical blocks. Start addressselector 60 selects the screen starting address, or the block startaddress. The screen starting address is the address location of thefirst pixel on the screen, usually the upper-left pixel of the top line.The block start address is the address of the first pixel in the nextphysical block of the display frame buffer. A hardware selector can beused to select the proper start address for start address selector 60,or a program or firmware can load the proper start address at thedesired time.

Just before the start of a new screen, VS is activated, and the screenstarting address from selector 60 is fed through mux 62 to line startregister 64. Otherwise, mux 62 selects the next line starting address,LSA(n+1), when the vertical sync VS is not active. This allows theaddress for the next horizontal line of pixels to be generated.

The new screen address (SSA) selected by mux 62 can be loaded into linestart register 64 when both HS and VS are active. Then, after the end ofthe horizontal sync (HS), the screen start address (SSA) in the linestart register 64 is latched into memory address counter 66 at the endof the horizontal sync.

Memory address counter 66 is incremented by the pixel size for eachpixel clock PCLK during the display time, when both horizontal displayactive HDA and vertical display active VDA are on. Memory addresscounter 66 is loaded with the line start address from line startregister 64 before the beginning of each line towards the end of the HStiming after line start register 64 is loaded with a new value at thebeginning of HS. Memory address counter 66 contains a physical addressthat is sent the physical memory to fetch the next pixel. The physicaladdress is in the on-chip SRAM for the first block, but can be in theexternal SDRAM for other blocks of the frame buffer.

Adder 70 generates the next line's starting address, LSA (n+1), byadding the current line start address from line start register 64 to thescreen-image width SIW from screen-width register 68. Screen-widthregister 68 contains the width of the screen, which is the number ofpixels in the displayed line plus the number of pixels in the off-screen(non-displayed) part of the line, multiplied by the pixel width in bytes(or other addressable units of the physical memory). This next-linestarting address is selected by mux 62 to be loaded into line startregister 64 at the beginning of the next HS.

The physical address of the current pixel from memory address counter 66is compared by detector 72 to the block end address BEA in register 76.When the current pixel's address matches the block end address, the endof the block has been reached. The next pixel must be fetched from adifferent physical block, which may not be contiguous with the currentblock.

Sometimes the block end may occur at the end of a line of pixels, orbetween the address at the end of a line and the next line's startaddress, rather than in the middle of the line. Then the block end isnot detected by detector 72. Instead, comparator 74 detects that thenext line's starting address (which is generated by adder 70) is greaterthan the block end address from BEA register 76.

When the end of the block is detected by either detector 72 (block endsin the middle of a line) or comparator 74 (block ends at end of line),block end signal BE is activated. The next-line address from adder 70 isno good as it over-runs or exceeds the end of the block. Instead, thestart address of the next block is used. This block start address (BSA)is selected to be output from start address selector 60 prior to the endof the current block. Mux 62 selects the new block's start address fromstart address selector 60 when BE is activated. The new block startaddress is latched into line start register 64 by the BE signal duringthe vertical display active time VDA.

Memory address counter 66 is loaded with the new block start addressfrom line start register 64. The next pixel in the line is fetched fromthe new physical memory block at this block starting address. Memoryaddress counter 66 then continues to count up with the pixel clock,reading pixels from the new physical block. Adder 70 generates the nextline's starting address, LSA(n+1) from the block's starting address inline start register 64. At the end of the line, when HS is activated,this new line's address is latched into line start register 64 throughmux 62, and pixel fetching continues with the second display line in thenew physical block.

The screen starting address in start address selector 60 is a full-widthaddress. The full address can be loaded into both the upper (U) andlower (L) portions of line start register 64 and memory address counter66 as described above. This allows the physical blocks to have anarbitrary length. However, the block start address uses a fixed blocksize, such as fixed-size pages. For example, the page size (length) isoften set to 4K bytes, where the lower 12 address bits are the offsetwithin the page. Then the page's (block's) starting address can bespecified by just the upper m−12 address bits, where m is the addresswidth in bits. For example, a 32-bit address can use just the upper 20bits as the page starting address, since it is assumed that the loweraddress bits are all zero's for the first address in the page.

Using such fixed-length physical-memory blocks, or pages, isadvantageous because smaller-width registers and logic paths can beused. Lower address bits can be quickly zeroed out when a new physicalblock is started. When a new block address is loaded from start addressselector 60 through mux 62 to line start register 64, the upper bits areloaded from start address selector 60 by mux 62 into the upper portionof line start register 64. The lower bits are zeroed by mux 62 andloaded as zeros into the lower portion of line start register 64.Likewise, the lower portion of memory address counter 66 can become zeroat the start of a new block, and just the upper bits loaded from linestart register 64. If the block end occurs between the end of a line andthe next start address, the lower portion of memory address counter 66can be loaded from output of the adder 70 through mux 62 and line startregister 64. This is not the start of a new block, so just the upperbits loaded from line start register 64.

Since all physical addresses within a block have the same upper addressbits, the upper portions of line start register 64 and memory addresscounter 66 can continue to be loaded from start address selector 60 foreach new line, if the next line start address is in the same block.Alternately, the upper portions can be loaded just once at the start ofthe block, and not re-loaded when the lower-portions are loaded for eachnew display line.

An overflow or carry-out signal from the lower portion of memory addresscounter 66 is an input to detector 72. If the block end address register76 and upper portion of memory address counter 66 are equal, then the BEsignal become active. Adder 70 outputs the next line's start memoryaddress which is input to comparator 74 to compare with block endaddress register 76 to signal the block end BE when the next line'sstart address is greater than block end address register 76.

Block Ends in Middle of Display Line—FIG. 6

FIG. 6 is a display timing diagram showing a block ending in the middleof a display line. Just two physical blocks are shown for clarity, butmore blocks could be used in an actual system. Pixels are written to thedisplay from the upper left to the upper right in the first line (LSA0),and then for other lines from top to bottom.

The displayable area occurs for only a portion of the total frame time.Pixels are written to the display during the horizontal display activeHDA time of a line, but not when HDA is off at the end of each line. Thehorizontal sync signal HS occurs when HDA is off at the ends of thelines.

Displayable lines of pixels are written to the display during thevertical display active VDA time, but not after the last line is writtenand VDA is turned off. Then the vertical sync VS signal occurs. Both theVS and HS signals are active near the end of the display frame timing.

The first physical block A, display block 46, begins with the screenstarting address SSA at the beginning of line LSA0, and ends with BEA online LSA(n). Block 46 ends in the middle of line LSA(n). Block-endsignal BE is activated by the detector when the memory address countermatches the block-end address. Then the starting address of the nextphysical block is loaded into the line start register.

The first pixel in the second physical block B is read from the blockstart address BSA and written to the display to continue the currentline LSA(n). Then other pixels in line LSA(n) in block 48 are written,and the next line LSA(n+1) in block 48 and subsequent lines are written.

Block Ends after End of Display Line in Off-Screen Area—FIG. 7

FIG. 7 is a display timing diagram showing a block ending after the endof a display line in the off-screen area. The first physical block A,display block 46, begins with the screen starting address SSA at thebeginning of line LSA0, and ends with BEA in the off-screen portion ofline LSA(n). Block 46 ends in the off-screen portion of line LSA(n),after HDA ends. The memory address can skip from the end of line N toLSA (N+1). There might be no actual memory accesses to the address BEAand BSA.

Block-end signal BE is activated by the comparator when the next-linestarting address generated by the adder exceeds the block-end address.Then the upper portion (U), bits m−12, of the next-line addressgenerated by adder 70 is discarded. Instead, the upper portion (U) ofthe starting address of the next physical block is loaded into the linestart register from start address selector 60. The lower part (L), bits11−0, generated by adder 70 is loaded to memory address counter 66through mux 62 and line start address register 64.

The first pixel in the second physical block B is read and written usingthe address value from memory address counter 66. It is the firstdisplayable pixel in the next line LSA(n+1). Then other pixels in lineLSA(n+1) in block 48 are written, and subsequent lines are written.

Full-Power Mode Fetches Pixels from Both On-Chip and ExternalMemories—FIG. 8A

FIG. 8A shows a display that is refreshed with pixels from the on-chipSRAM and from the external SDRAM. The first physical block A begins withthe screen start address SSA and is a block in the on-chip SRAM. Thesememory accesses require less power since no off-chip signals are driven.Access times can be faster. First block 46 continues until the block endaddress BEA.

The second block B of the frame buffer begins at block start addressBSA. Second block 48 continues to the end of the displayable area inthis simplified example. This second block 48 is stored in externalSDRAM, which requires more power to access than the on-chip SRAM sinceexternal lines with larger capacitances have to be driven. Also, theaccess time may be slower for the external SDRAM than for the internalSRAM.

During display of a frame, power consumption of the graphics functionsin the SOC chip is lower during first block 46 than for second block 48and any subsequent blocks from external SDRAM.

Low-Power Mode Fetches Pixels only from On-Chip Memory—FIG. 8B

FIG. 8B shows a reduced-size display mode that is refreshed with pixelsfrom the on-chip SRAM. The first physical block A begins with the screenstart address SSA and is a block in the on-chip SRAM. First block 46continues until the block end address BEA. The second block B of theframe buffer begins at block start address BSA and continues to the endof the full display. This second block 48 is stored in external SDRAM,which requires more power to access than the on-chip SRAM since externallines with larger capacitances have to be driven.

To save power, the size of the display is reduced to a display windowthat is a fraction of the normal display. Additional counters andcomparators count the number of pixels in the current line, and the linenumber. When the number of pixels in the current line matches or exceedsthe horizontal-active-end HAE value, memory fetching ends for the line.Instead, dummy pixel data is written to the display. The dummy pixelscould all be black or gray or some other pre-determined color. Thesedummy pixels form blank data 82 that is displayed after HAE. Active data80 contains pixels that are fetched from the on-chip SRAM.

When the current line matches or exceeds the vertical-active end (VAE),memory fetching for the frame ends. Dummy pixels are written to thedisplay, forming blank data 84.

The values for HAE and VAE are set so that the display window of activedata 80 falls completely within first block 46, before BEA. Only dummypixel data occurs in the second block 48, and no pixel-fetches of theexternal memory are required.

During display of a frame in a stand-by or other low-power mode usingonly the display window, power consumption of the graphics functions inthe SOC chip is lower since only pixels from first block 46 are fetched.No fetches occur for second block 48, so power-hungry fetches fromexternal SDRAM are eliminated.

Active data 80 in the smaller display window can contain statusinformation for the hand-held device, or a smaller amount of informationthan is available for the full-power mode when the entire display iswritten. The hand-held device can switch to the standby or low-powerdisplay mode when the battery is low, or when little activity isoccurring. The device can switch to the higher or full-power mode whenthe user is actively operating the device and needs more informationdisplayed.

ALTERNATE EMBODIMENTS

Several other embodiments are contemplated by the inventors. For examplethe address generator of FIG. 5 could be implemented in logic gates andregisters, or programmably implemented, or some combination of dedicatedhardware and firmware. Other kinds of address translation could besubstituted, or paging could be implemented in a variety of ways.

The entire page (all offset address locations within a page) does nothave to be used by displayable pixels. Some overhead storage locationsmay be located on the page, and the last page on a frame can have onlysome of the available space used. A typical system has many more pagesthan shown in the drawings. For example, a frame buffer that stores 1M-byte of pixels uses about 256 physical pages when each page is 4K inlength.

The physical address of the memory may be specified in units other thanbytes. For example, the physical memory may be read in words of 4 or 8bytes. The memory address counter can be made to increment by one memoryword every other pixel clock, to fetch several pixels at a time. Memoryaddress counter 66 could count downward rather than upward to readblocks from top to bottom.

Some systems may not use vertical and horizontal sync signals, or othertiming signals described, or may substitute other signals. Flat-paneland LCD displays may not require sync signals, or may use other signals.However, the invention can be modified to use these substitute signals,or dummy sync signals can be generated. The pixel clock may be stoppedwhile the memory address counter is loaded, or pixel buffering or fastaddress loading may allow the pixel clock to continue uninterrupted.

The hand-held device can switch to a lower-power mode by changing thecolor resolution of the display. For example, the display can beswitched from a 2 byte per pixel mode to a 2-bit per pixel mode toreduce the frame buffer size and reduce memory fetches. The number ofpixels per line, and the numbers of lines per frame may also be changedto reduce power. When the frame buffer size falls below the size of theon-chip SRAM, then a refresh fetches are to the lower-power on-chipmemory. Even when some external memory is needed, reducing the overallframe-buffer size reduces the number of external fetches needed and thusreduces power.

The abstract of the disclosure is provided to comply with the rulesrequiring an abstract, which will allow a searcher to quickly ascertainthe subject matter of the technical disclosure of any patent issued fromthis disclosure. It is submitted with the understanding that it will notbe used to interpret or limit the scope or meaning of the claims. 37C.F.R. §1.72(b). Any advantages and benefits described may not apply toall embodiments of the invention. When the word “means” is recited in aclaim element, Applicant intends for the claim element to fall under 35USC §112, paragraph 6. Often a label of one or more words precedes theword “means”. The word or words preceding the word “means” is a labelintended to ease referencing of claims elements and is not intended toconvey a structural limitation. Such means-plus-function claims areintended to cover not only the structures described herein forperforming the function and their structural equivalents, but alsoequivalent structures. For example, although a nail and a screw havedifferent structures, they are equivalent structures since they bothperform the function of fastening. Claims that do not use the word meansare not intended to fall under 35 USC §112, paragraph 6. Signals aretypically electronic signals, but may be optical signals such as can becarried over a fiber optic line.

The foregoing description of the embodiments of the invention has beenpresented for the purposes of illustration and description. It is notintended to be exhaustive or to limit the invention to the precise formdisclosed. Many modifications and variations are possible in light ofthe above teaching. It is intended that the scope of the invention belimited not by this detailed description, but rather by the claimsappended hereto.

What is claimed is:
 1. A multi-block display-refresh controllercomprising: a start address selector for selecting a block startingaddress from a plurality of block starting addresses and a screenstarting address, the start address selector being loaded with a seriesof block starting addresses for a plurality of blocks within a displayframe; a selector, coupled to the start address selector, for selectingeither the block starting address or a next-line address for output; aline start register, coupled to receive an output of the selector, forstoring a line starting address for a horizontal line of pixels in thedisplay frame; a memory address counter that is loaded with the linestarting address from the line start register and incremented by a pixelclock as pixels in the horizontal line are written to a display; anadder, receiving the line starting address from the line start register,for adding a line width to the line starting address to generate thenext-line address to the selector; a block-end detector, coupled toreceive a pixel address from the memory address counter, for detecting ablock end when the pixel address matches a block-end address for acurrent one of the plurality of blocks within the display frame; andwherein the selector selects a new block starting address from the startaddress selector when the block-end detector detects the block end, butthe selector selects the next-line address from the adder when the blockend is not detected by the block-end detector, whereby new blockstarting address are used when block ends are detected as the pluralityof blocks of pixels are displayed within a display frame.
 2. Themulti-block display-refresh controller of claim 1 wherein when the blockend is detected the line start register is loaded from the selector andthe memory address counter is loaded from the line start register usinga new block starting address from the start address selector, wherebypixel addresses are re-loaded when the block end is detected.
 3. Themulti-block display-refresh controller of claim 2 wherein the block endcan occur in a middle of a horizontal line of pixels, wherein pixelsfrom two blocks are displayed on a same horizontal line, wherein the twoblocks are in non-adjacent memory locations separated by other data. 4.The multi-block display-refresh controller of claim 3 wherein the blockend can also occur at an end of the horizontal line; further comprising:a comparator, receiving the next-line address from the adder, forcomparing the next-line address to the block-end address and signalingthe block end when the next-line address exceeds the block-end address.5. The multi-block display-refresh controller of claim 4 wherein thestart address selector is repeatedly over-written with a new blockstarting address as the series of blocks of pixels in the display frameare read; wherein the block-end address is stored in a block-endregister that is repeatedly over-written with a new block-end addressfor the block that had a block starting address in the start addressselector.
 6. A portable system comprising: execute means for executingprograms that write pixels for display to a single-block frame buffer;frame-buffer-address translate means, receiving addresses of pixels fromthe execute means, for translating the addresses of pixels to memoryaddresses in a plurality of physical memory blocks; low-power memorymeans for storing some of the plurality of physical memory blocks thatstore pixels; high-power-memory access means for reading pixels storedin others of the plurality of physical memory blocks that are stored inan external memory; wherein accesses of pixels stored in the externalmemory consume more power than accesses of pixels stored in thelow-power memory means; and display controller means for writing pixelsto a display, the display controller means reading pixels stored in theplurality of physical memory blocks including reading pixels stored inthe low-power memory means and pixels stored in the external memory;wherein the display controller means further comprises: pixel countermeans, having a pixel address that is incremented in response to a pixelclock as pixels are read from the lower-power memory means or from theexternal memory; block-end register means for storing a block-endaddress of a current block in the plurality of physical memory blocks;block-start register means for storing a block-start address of thecurrent block in the plurality of physical memory blocks; block-enddetect means for detecting a block end when the pixel address from thepixel counter means reaches the block-end address from the block-endregister means; select means for loading the pixel counter means with anext block-start address from the block-start register means when theblock-end detect means detects the block end, line start register means,loaded by the select means with the next block-start address when theblock end is detected, for storing a starting pixel address for adisplay line; and add means, receiving the starting pixel address fromthe line start register means, for adding a line-width of pixels togenerate a next-line starting pixel address to be loaded into the linestart register means at an end of the display line; whereby pixels inthe single-block frame buffer are stored in multiple physical blocks inboth the low-power memory means and in the external memory and wherebythe pixel counter means is re-loaded with the next block-start addresswhen the block end is detected.
 7. The portable system of claim 6wherein the low-power memory means is a memory on a same substrate asthe execute means and the display controller means, but the externalmemory is on a separate substrate.
 8. The portable system of claim 6wherein the display controller means can enter a low-power mode whereinpixels are fetched only from the low-power memory means but not from theexternal memory, the display controller means can also enter ahigh-power mode wherein pixels are fetched from both the low-powermemory means and from the external memory; wherein the high-power modeconsumes more power that the low-power mode.
 9. The portable system ofclaim 6 further comprising: window means, in the display controllermeans, for detecting when a current location for pixel fetching reachesa window limit, the window means preventing memory accesses to fetchpixels after the window limit is reached but instead supplying a fixedpixel for display, whereby fixed pixels rather than memory-fetchedpixels are displayed once the window limit is reached.
 10. An integratedcircuit capable of being coupled, during use, to an external memory thatis separate from the integrated circuit, the integrated circuitcomprising: a memory configured to store a first memory block of a framebuffer that comprises a plurality of memory blocks in a full power mode,wherein at least one of the other memory blocks of the plurality ofmemory blocks are stored in the external memory in the full power mode;and a display controller coupled to the memory and configured to readpixels from the memory to be displayed on a display screen, and wherein,in a low power mode, the display controller is configured to displaypixels read from the frame buffer on a reduced window of the displayscreen that excludes a portion of the display screen, and wherein thedisplay controller is configured to read the displayed pixels for thereduced window only from the first memory block in the memory, andwherein the display controller is configured to display a fixed pixelnot read from the memory or the external memory for the remaining pixelson the display screen outside of the reduced window, and wherein, in thefull power mode, the display controller is configured to read pixels tobe displayed from both the memory and the external memory.
 11. Theapparatus as recited in claim 10 wherein the display controllercomprises a pixel counter configured to count a number of pixels from acurrent display line that have been displayed, and wherein the displaycontroller is configured to fetch pixels from the memory for displayuntil the counter reaches an end of the reduced window, and wherein thedisplay controller is configured to display the fixed pixel for theremainder of the current display line.
 12. The apparatus as recited inclaim 11 wherein the remainder of the current display line is mapped toaddresses in the memory, but the display controller is configured todisplay the fixed pixel responsive to the counter reaching the end ofthe reduced window.
 13. The apparatus as recited in claim 12 wherein thedisplay controller is configured to not fetch the pixels correspondingto the remainder of the current display line from the memory.
 14. Theapparatus as recited in claim 10 wherein the display controllercomprises a line counter configured to indicate a line number of thecurrent display line, and wherein the display controller is configuredto display only the fixed pixel for remaining display lines when theline number reaches an end of the reduced window.
 15. The apparatus asrecited in claim 14 wherein pixels from one or more of the remainingdisplay lines are mapped to addresses in the memory, but the displaycontroller is configured to display the fixed pixel responsive to thecounter reaching the end of the reduced window.
 16. The apparatus asrecited in claim 15 wherein the display controller is configured to notfetch the pixels corresponding to the remaining display lines from thememory.
 17. A method comprising: in a low power mode, displaying pixelsread from a frame buffer on a reduced window of a display screen thatexcludes a portion of the display screen, wherein the displayingcomprises: reading the displayed pixels for the reduced window only froma first block in a memory included on a same integrated circuit as adisplay controller that performs the displaying; and displaying a fixedpixel not read from the memory or the external memory for the remainingpixels on the display screen outside of the reduced window; and in afull power mode, displaying pixels read from both the memory and anexternal memory coupled to the integrated circuit.
 18. The method asrecited in claim 17 further comprising, in the low power mode,displaying a different image on the reduced window than is displayed ona full window that includes the frame buffer data from the memory andfrom the external memory.
 19. The method as recited in claim 18 whereinthe different image comprises status data for a device that includes theintegrated circuit.
 20. The method as recited in claim 18 wherein thedifferent image comprises a smaller amount of information than isdisplayed in a full power mode.
 21. The method as recited in claim 17further comprising: detecting that pixels displayed from the currentdisplay line have reached an end of the reduced window; ceasing fetchingpixels from the memory for display responsive to the detecting; anddisplaying the fixed pixel for the remainder of the current displayline.
 22. The method as recited in claim 21 wherein the remainder of thecurrent display line is mapped to addresses in the memory, but the fixedpixel is displayed.
 23. The method as recited in claim 17 furthercomprising: detecting that the current display line is an end of thereduced window; ceasing fetching pixels from the memory for displayresponsive to the detecting; and displaying the fixed pixel for theremaining display lines.
 24. The method as recited in claim 23 whereinpixels from one or more of the remaining display lines are mapped toaddresses in the memory, but the fixed pixel is displayed.
 25. Aportable device comprising: a display screen; and an integrated circuitcoupled to the display screen, wherein the integrated circuit comprises:a memory configured to store a first memory block of a frame buffer thatcomprises a plurality of memory blocks in a full power mode, wherein atleast one of the other memory blocks of the plurality of memory blocksare stored in an external memory separate from the integrated circuit inthe full power mode; and a display controller coupled to the memory andconfigured to read pixels from the memory to be displayed on a displayscreen, and wherein, in a low power mode, the display controller isconfigured to display pixels read from the frame buffer on a reducedwindow of the display screen that excludes a portion of the displayscreen, and wherein the display controller is configured to read thedisplayed pixels for the reduced window only from the first memory blockin the memory, and wherein the display controller is configured todisplay a fixed pixel not read from the memory or the external memoryfor the remaining pixels on the display screen outside of the reducedwindow, and wherein, in the full power mode, the display controller isconfigured to read pixels to be displayed from both the memory and theexternal memory.
 26. The portable device as recited in claim 25 whereinthe portable device is a portable communication device.
 27. The portabledevice as recited in claim 25 wherein the portable device is a portablecomputing device.
 28. The portable device as recited in claim 25 furthercomprising the external memory coupled to the integrated circuit.